In an electric discharge machining apparatus, voltage pulses are repeatedly applied to a work gap formed between a tool electrode and a workpiece. The work gap is generally filled with dielectric fluid, and has a size of a few μm to a few tens of μm. Electric discharge or sparking is caused in the work gap as a result of the application of voltage pulses, and the electric discharge machining apparatus normally detects the electric discharge electrically. Patent documents 1-5 disclose an electric discharge machining apparatus provided with an electric discharge detector or electric discharge detection circuit.
A period from application of voltage pulses to the occurrence of electric discharge is called delay time. The delay time has an undefined value, including zero. Together with the occurrence of electric discharge, current starts to flow via the work gap. Once a specified period (“on-time”) elapses from the occurrence of electric discharge, supply of current is stopped. Once a specified period (“off-time”) elapses from completion of the on-time, a voltage pulse is again applied to the work gap. On-time and off-time are important parameters controlled by an NC device of an electric discharge machining apparatus. A term “NC” may refer to numerical control or numerically controlled.
A conventional electric discharge machining apparatus provided with an electric discharge detector will be described with reference to FIGS. 4-8. As shown in FIG. 4, a microscopic work gap 12 is formed between a tool electrode 11 and a workpiece 10. A first series combination comprising a dc power source 4, current limiting resistor 7 and switching element 8 is connected to the work gap 12. The voltage of the dc power source 4 is set between 60V and 150V. A second series combination comprising a dc power source 5, current limiting resistor 6 and switching element 9 is connected to the work gap 12, in parallel with the first series combination. The voltage of the dc power source 5 is set between 90V and 280V. A potential divider having a pair of resistors 13, 14 detects a voltage Vgap across the work gap 12. The gap voltage Vgap is supplied to an electric discharge detector 3.
The ON/OFF switching operation of switching elements 8 and 9 is controlled by a gate signal Gate. A gate signal generator 2 generates the gate signal Gate, and the gate signal Gate is also supplied to the electric discharge detector 3. Data ON_Data for on time command and data OFF_data for off time command are generated within an NC device 1 and supplied to the gate signal generator 2. The NC device 1 also supplies data Vref_Data, representing a reference voltage, to the electric discharge detector 3. The electric discharge detector 3 supplies an electric discharge detection signal spark, representing electric discharge, to the gate signal generator 2.
One example of a gate signal generator will be described with reference to FIG. 5. A gate signal generator 2 is comprised of a selector 23, AND gate 25, counter 20, comparator 21, selector 22 and T-flipflop 24. A clock signal CLK1 is sent to the selector 23 via the AND gate 25. The AND gate 25 only passes the clock signal CLK 1 when the signal spark is on. Also, a clock signal CLK2 is sent to the selector 23. The selector 23 alternately supplies clock signal CLK1 as signal ON_CLK or clock signal CLK2 as signal OFF_CLK to the counter 20. The counter 20 counts the signal ON_CLK or the signal OFF_CLK. A Q output of the counter 20 is connected to an input A of the comparator 21. On time command data ON_Data and off time command data OFF_Data are supplied to the selector 22. An 0 output of the selector 22 is connected to an input B of the comparator 21. Output A=B of the comparator 21 is connected to the reset input RES of the counter 20 and the input T of the T-flipflop 24. The T-flipflop 24 generates the signal Gate for the switching elements 8 and 9. The signal Gate is also supplied to the input S of the selector 22 and to the selector 23.
An operation of the gate signal generator 2 will be described with reference to FIG. 6. If the on time command data ON_Data is set to “6”, and the off time command data OFF_Data is set to “4”, then: at time t1, if a count of the signal OFF_CLK reaches “4” in the counter 20, then the comparator 21 generates pulse A=B, as shown in FIG. 6(A). As a result of the pulse A=B the count of “4” in the counter 20 is reset to “0”, and as shown in FIG. 6(B) the T-flipflop 24 changes the level of the signal Gate from “0” to “1”. In response to the signal Gate at level “1”, the voltages of the dc power sources 4 and 5 are applied to the work gap 12. Further, the selector 23 selects the signal ON_CLK, while the selector 22 selects the on time command data ON_Data.
At time t2 when an undefined delay time tw has elapsed from time t1, the electric discharge detection signal spark becomes on, as shown in FIG. 6(C). As shown in FIG. 6(D), the counter 20 starts a count of the signal ON_CLK. At time t3, if a count of the signal ON_CLK reaches “6” in the counter 20, then the comparator 21 generates pulse A=B, as shown in FIG. 6(A). As a result of the pulse A=B the count of “6” in the counter 20 is reset to “0”, and as shown in FIG. 6(B) the T-flip-flop 24 changes the level of the signal Gate from “1” to “0”. In response to the signal Gate at level “0”, the switching elements 8 and 9 are turned off and application of voltage to the work gap 12 is stopped. Further, the selector 23 selects the signal OFF_CLK, while the selector 22 selects the off time command data OFF_Data. As shown in FIG. 6(E), the counter 20 starts a count of the signal OFF_CLK. At time t4, if a count of the signal OFF_CLK again reaches “4” in the counter 20, then the comparator 21 generates pulse A=B, as shown in FIG. 6(A).
One example of an electric discharge detector will be described with reference to FIG. 7. An electric discharge detector 3 is comprised of a reference voltage generator 31, a comparator amplifier circuit 34, and an AND gate 35. The NC device 1 supplies data Vref_Data representing a reference voltage to the reference voltage generator 31. The data Vref_Data is determined according to setting of conditions such as voltage of the dc power sources 4 and 5. The reference voltage generator 31 generates a reference voltage Vref according to the data Vref_Data. A gap voltage Vgap is supplied via a protection resistor 32 to one terminal of the comparator amplifier circuit 34. The reference Vref is supplied via a protection resistor 33 to the other terminal of the comparator amplifier circuit 34. The comparator amplifier circuit 34 compares the gap voltage Vgap and the reference voltage Vref, and generates a binary signal CP. The signal CP is on when the gap voltage Vgap is lower than the reference signal Vref. When the signals Gate and CP are on, the signal spark, which is the output of the AND gate 35, is on.
An operation of the electric discharge detector 3 will be described with reference to FIG. 8. The voltage waveform on the left side of FIG. 8 is for when only the 80V dc power source 4 is used. As shown in FIG. 8(D), at time t0, if the signal Gate becomes on, the gap voltage Vgap begins to rise as shown in FIG. 8(A). At time t1 when the gap voltage Vgap reaches the reference voltage Vref, the signal CP turns off, as shown in FIG. 8(C). At time t2 when electric discharge has started, the gap voltage Vgap starts to fall, as shown in FIG. 8(A), and current Igap flows via the work gap 12, as shown in FIG. 8(B). At time t3 when the gap voltage Vgap becomes lower than the reference voltage Vref, the signal CP becomes on, as shown in FIG. 8(C), and the signal spark also becomes on, as shown in FIG. 8(E). In this manner the increase in the electric discharge detection signal spark is delayed by the delay time td1 from time t2 to time t3. At time t4 when the on time command has elapsed from time t3, the signal Gate becomes off, as shown in FIG. 8(D), and the signal spark also becomes off, as shown in FIG. 8(E). At time t5 the gap current Igap becomes zero, as shown in FIG. 8(B).
The right side of FIG. 8 shows a typical waveform that appears in the case where a workpiece 10 having a high specific resistance is machined. In this case both dc power sources 4 and 5 are used, and a high voltage of about 150V is applied to the work gap 12. At time t6 when the signal Gate becomes on, as shown in FIG. 8(D), the gap voltage Vgap begins to rise, as shown in FIG. 8(A). At time t7 the gap voltage Vgap starts to fall. At time t8 when the gap voltage Vgap becomes lower than the reference voltage Vref, the signal spark becomes on, as shown in FIG. 8(E). However, a delay time td2 in increasing the signal spark, that is from time t7 to time t8, becomes larger than the delay time td1. With these types of delay times td1 and td2, there is lack of highly precise control of the on time, that is particularly required in microfabrication.    Patent Document 1: Japanese Patent No. 44-13195    Patent Document 2: Japanese Patent No. 3582370, FIG. 14-15    Patent Document 3: Japanese Patent No. 3396515    Patent Document 4: Japanese Laid-open Patent application No. 2001-038527    Patent Document 5: Japanese Patent No. 46-24678